Modern electronic devices, and particularly, integrated circuits, are at risk of damage due to electrostatic discharge (ESD) events. During an ESD event, a voltage (or current) may be provided to one or more terminals of an electronic device that causes the voltage between those terminals to exceed the designed maximum voltage of the device, which could impair subsequent operation of the device. For example, a voltage at a terminal of an electronic device during an ESD event may exceed the breakdown voltage of one or more components of the device, and thereby potentially damage those components. Accordingly, electronic devices include discharge protection circuitry that provides protection from excessive voltages across electrical components during ESD events.
To avoid interfering with normal operation of the device being protected, the discharge protection circuitry is typically designed to turn on and conduct current when the applied voltage exceeds the operating voltage of the device but before the applied voltage exceeds the breakdown voltage of the device. In practice, there is often a difference between the transient triggering voltage and the steady state (or direct current) breakdown voltage of the discharge protection circuitry. However, this voltage difference can make it difficult for the discharge protection circuitry to fit within the design window defined by the respective operating and breakdown voltages of the device to be protected (or alternatively, constrains the circuit designer to operating and breakdown voltages that accommodate the difference in triggering voltages of the protection circuitry). Additionally, when multiple instances of the discharge protection circuitry are used to provide a higher level of ESD voltage protection, the difference between transient triggering voltage and steady state breakdown is multiplied, which further constrains circuit designers.
Existing discharge protection circuitry may also be susceptible to latchup or otherwise exhibit snapback behavior, where parasitics within the discharge protection circuitry continue to conduct current at the design voltage, and thereby impair the functionality of the discharge protection circuitry after an ESD event. Thus, another concern when designing ESD protection devices is providing a snapback (or holding) voltage that exceeds the design voltage so that the ESD protection device stops conducting current when the applied voltage falls to the design voltage after an ESD event.